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As an STA Engineer in DRAM and Emerging memory Group (DEG), you will be responsible for designing and verifying Functional Blocks used in the development of memory products.
This includes simulating, optimizing, and timing analysis when deploying into DRAM circuits. In this position you will work and support the efforts of groups such as DEG Design / Verification to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction.
Responsibilities will include, but are not limited to, the following :
Build function and timing models for standardized and customized logic design
Perform Static Timing Analysis on the memory control logic design with industry lead EDA tools
Deploy the RTL-IP with the standardized flow and continue improving the flow for high quality
Supporting the RTL-IP user for layout process including floor-planning, placement, and routing
Perform verification processes with modeling and simulation using industry standard simulators
Maintain technical expertise and provide training
Contribute to cross group communication to work towards standardization and group success
Proactively solicit input from Standards, CAD, modeling, and verification groups to ensure the design quality
Drive innovation into the future Memory generation with dynamic work environment
Successful candidates for this position will have :
Rich experience in STA and making timing constrains based on Primetime or it’s counterparts
Experience in taking an industrial specification and implementing the respective IP
Good understanding on timing / area / power / complexity tradeoffs on complex interface design
Familiar with IP level verification and strong RTL debugging capabilities
Experience in frontend implementation tasks such as synthesis and logic equivalence
Experience in large scale mix signal circuitry design including logic implementation / verification, timing analysis / optimization an advantage
Experience in ASIC backend flow with parasitic extraction and timing closure is a plus
Experience in liberty / Verilog model characterization is a plus
Excellent problem-solving and analytical skills
A self-motivated, enthusiastic team player who enjoys working with others
Good communication skills with the ability to convey complex technical concepts to other design peers in verbal and written form
Education (One of the following is required)
A Bachelor in Electrical Engineering or related discipline plus 5+ years of experience.
A Master in Electrical Engineering or related discipline plus 3+ years of experienceAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.